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CY7C107BN CY7C1007BN
1M x 1 Static RAM
Features
* High speed -- tAA = 15 ns * CMOS for optimum speed/power * Automatic power-down when deselected * TTL-compatible inputs and outputs
Functional Description
The CY7C107BN and CY7C1007BN are high-performance CMOS static RAMs organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW Chip Enable (CE) and three-state drivers. These devices have an automatic power-down feature that reduces power consumption by more than 65% when deselected. Writing to the devices is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the input pin (DIN) is written into the memory location specified on the address pins (A0 through A19). Reading from the devices is accomplished by taking Chip Enable (CE) LOW while Write Enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the data output (DOUT) pin. The output pin (DOUT) is placed in a high-impedance state when the device is deselected (CE HIGH) or during a write operation (CE and WE LOW). The CY7C107BN is available in a standard 400-mil-wide SOJ; the CY7C1007BN is available in a standard 300-mil-wide SOJ
Logic Block Diagram
DIN
Pin Configuration
SOJ Top View A10 A11 A12 A13 A14 A15 NC A16 A17 A18 A19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15
INPUT BUFFER A0 A1 A2 A3 A4 A5 A6 A7 A8 ROW DECODER SENSE AMPS
512 x 2048 Y ARRA
DOUT
DOUT WE GND
VCC A9 A8 A7 A6 A5 A4 NC A3 A2 A1 A0 DIN CE
COLUMN DECODER A9 A 10 A 11 A 12 A 13 A 14 A 15 A 16 A 17 A 18 A 19
POWER DOWN
CE WE
Selection Guide
7C107BN-15 7C1007BN-15 15 80 2
Maximum Access Time (ns) Maximum Operating Current (mA) Maximum CMOS Standby Current ISB2 (mA)
Cypress Semiconductor Corporation Document #: 001-06426 Rev. **
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised February 1, 2006
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Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ..................................-65C to +150C Ambient Temperature with Power Applied..............................................-55C to +125C Supply Voltage on VCC Relative to GND[1] ..... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[1] .................................... -0.5V to VCC + 0.5V DC Input Voltage[1]..................................-0.5V to VCC + 0.5V Current into Outputs (LOW)......................................... 20 mA Static Discharge Voltage............................................ >2001V (per MIL-STD-883, Method 3015) Latch-Up Current ..................................................... >200 mA
Operating Range
Range Commercial Industrial Ambient Temperature[2] 0C to +70C -40C to +85C VCC 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
7C107BN-15 7C1007BN-15 Parameter VOH VOL VIH VIL IIX IOZ IOS ICC ISB1 ISB2 Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage[1] GND < VI < VCC GND < VI < VCC, Output Disabled VCC = Max., VOUT = GND VCC = Max., IOUT = 0 mA, f = fMAX = 1/tRC Max. VCC, CE > VIH, VIN >VIH or VIN < VIL, f = f MAX Max. VCC, CE > VCC - 0.3V, VIN > VCC - 0.3V or VIN < 0.3V, f = 0 Test Conditions VCC = Min., IOH = -4.0 mA VCC = Min., IOL = 8.0 mA 2.2 -0.3 -1 -5 Min. 2.4 0.4 VCC + 0.3 0.8 +1 +5 -300 80 20 2 Max. Unit V V V V mA mA mA mA mA mA
Input Leakage Current Output Leakage Current Output Short Circuit Current[3] VCC Operating Supply Current Automatic CE Power-Down Current-- TTL Inputs Automatic CE Power-Down Current -- CMOS Inputs
Capacitance[4]
Parameter CIN: Addresses CIN: Controls COUT Output Capacitance Description Input Capacitance Test Conditions TA = 25 x C, f = 1 MHz, VCC = 5.0V Max. 7 10 10 Unit pF pF pF
Notes: 1. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 2. TA is the "Instant On" case temperature. 3. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds. 4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 001-06426 Rev. **
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CY7C107BN CY7C1007BN
AC Test Loads and Waveforms
5V OUTPUT 30 pF INCLUDING JIG AND SCOPE (a) R2 255 R1 480 5V OUTPUT 5 pF INCLUDING JIG AND SCOPE (b) R2 255 R1 480 3.0V GND 10% 3 ns ALL INPUT PULSES 90% 90% 10% 3 ns
Equivalent to: OUTPUT
THEVENIN EQUIVALENT 167 1.73V
Switching Characteristics[5] Over the Operating Range
7C107BN-15 7C1007BN-15 Parameter READ CYCLE tRC tAA tOHA tACE tLZCE tHZCE tPU tPD WRITE CYCLE tWC tSCE tAW tHA tSA tPWE tSD tHD tLZWE tHZWE
[8]
Description Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid CE LOW to Low Z[6]
Min. 15
Max.
Unit ns
15 3 15 3 7 0 15 15 12 12 0 0 12 8 0 3 7
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
CE HIGH to High Z[6, 7] CE LOW to Power-Up CE HIGH to Power-Down Write Cycle Time CE LOW to Write End Address Set-Up to Write End Address Hold from Write End Address Set-Up to Write Start WE Pulse Width Data Set-Up to Write End Data Hold from Write End WE HIGH to Low Z[6] WE LOW to High Z[6, 7]
Notes: 5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 30-pF load capacitance. 6. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE for any given device. 7. tHZCE and tHZWE are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 001-06426 Rev. **
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Switching Waveforms
Read Cycle No. 1[10, 11]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2[11, 12]
ADDRESS tRC CE tACE tLZCE DATA OUT HIGH IMPEDANCE DATA VALID tPD 50% 50% ICC ISB tHZCE HIGH IMPEDANCE
VCC SUPPLY CURRENT
tPU
Write Cycle No. 1 (CE Controlled)[13]
tWC ADDRESS tSA CE tAW WE tPWE tSD DATA IN DATA VALID tHD tHA tSCE
DATA OUT
HIGH IMPEDANCE
Notes: 9. No input may exceed VCC + 0.5V. 10. Device is continuously selected, CE = VIL. 11. WE is HIGH for read cycle. 12. Address valid prior to or coincident with CE transition LOW. 13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.
Document #: 001-06426 Rev. **
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CY7C107BN CY7C1007BN
Switching Waveforms (continued)
Write Cycle No. 2 (WE Controlled)[13]
tWC ADDRESS tSCE CE tSA WE tSD DATA IN DATA VALID tHZWE DATA OUT DATA UNDEFINED tLZWE HIGH IMPEDANCE tHD tAW tPWE tHA
Truth Table
CE H L L WE X H L High Z Data Out High Z DOUT Read Write Mode Power-Down Standby (ISB) Active (ICC) Active (ICC) Power
Ordering Information
Speed (ns) 15 Ordering Code CY7C107BN-15VC CY7C1007BN-15VC CY7C1007BN-15VXC CY7C107BN-15VI Package Diagram 51-85032 51-85031 51-85031 51-85032 Package Type 28-Lead (400-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ 28-Lead (300-Mil) Molded SOJ (Pb-free) 28-Lead (400-Mil) Molded SOJ Operating Range Commercial
Industrial
Please contact local sales representative regarding availability of these parts
Document #: 001-06426 Rev. **
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CY7C107BN CY7C1007BN
Package Diagrams
28-Lead (400-Mil) Molded SOJ (51-85032)
PIN 1 I.D
14
1
.395 .405
.435 .445
DIMENSIONS IN INCHES
MIN. MAX.
15
28
.720 .730 SEATING PLANE .128 .148 .050 TYP. .015 .020 .026 .032
0.004
.007 .013 .360 .380
51-85032.*B 51-85032-*B
.025 MIN.
28-Lead (300-Mil) Molded SOJ (51-85031)
NOTE : 1. JEDEC STD REF MO088 2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE 3. DIMENSIONS IN INCHES MIN. MAX.
PIN 1 ID
14 1
DETAIL A EXTERNAL LEAD DESIGN
0.291 0.300
0.330 0.350 0.013 0.019
OPTION 1 OPTION 2
0.026 0.032 0.014 0.020
15
28
0.697 0.713 0.120 0.140 0.050 TYP.
SEATING PLANE
0.007 0.013
0.004
A
0.025 MIN.
0.262 0.272
51-85031-*C
All product or company names mentioned in this document may be the trademarks of their respective holders. Document #: 001-06426 Rev. ** Page 6 of 7
(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY7C107BN CY7C1007BN
Document History Page
Document Title: CY7C107BN/CY7C1007BN 1M x 1 Static RAM Document Number: 001-06426 REV. ** ECN NO. 423847 Issue Date See ECN Orig. of Change NXR New Data Sheet Description of Change
Document #: 001-06426 Rev. **
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